TY  - JOUR
AU  - Zhou, Zijie
AU  - Jin, Xiangliang
AU  - Wang, Yang
AU  - Dong, Peng
AU  - Peng, Yan
AU  - Luo, Jun
PY  - 2021/02/25
Y2  - 2025/01/01
TI  - Analysis of Non-Uniform Current Distribution in Multi-Fingered and Low-Voltage-Triggered LVTSCR
JF  - Elektronika ir Elektrotechnika
JA  - ELEKTRON ELEKTROTECH
VL  - 27
IS  - 1
SE  - 
DO  - 10.5755/j02.eie.25352
UR  - https://eejournal.ktu.lt/index.php/elt/article/view/25352
SP  - 41-47
AB  - &lt;p&gt;Laterally Diffused Metal Oxide Semiconductor Silicon-Controlled Rectifier (LDMOS-SCR) is usually used in Electrostatic Discharge (ESD) protection. LDMOS-SCR discharges current by parasitic SCR, but the MOS in it cannot work when parasitic SCR is stabilized. To further enhance the Electrostatic Discharge (ESD) discharging capability of LDMOS-SCR, a novel high failure current LDMOS-SCR with 12 V operation voltage is fabricated and verified in a 0.18-um high-voltage Bipolar-CMOS-DMOS (BCD) process. Compared with conventional LDMOS-SCR, the novel LDMOS-SCR (LDMOS-SCR-R) introduced a heavily doped p-type region, which is located between the heavily doped n-type and p-type regions of Cathode and is connected with the gate. The adding p-well resistance can drop the voltage on the gate, and the gate with p-well resistance also has resistance and capacitance coupling effect. According to the results of the transmission line pulse test (TLP), the voltage applied to the gate by increasing the p-well resistance plays a major role in the device working mechanism. Under the same device size, LDMOS-SCR-R has higher &lt;em&gt;I&lt;sub&gt;t2&lt;/sub&gt;&lt;/em&gt; (8.6 A) than conventional LDMOS (2.21 A) or LDMOS-SCR (6.62 A) in TLP results. Compared with LDMOS-SCR, the failure current of LDMOS-SCR-R increases by 30 %, and the FOM of LDMOS-SCR-R increases by 34 %. The response of LDMOS-SCR-R is also faster than that of LDMOS-SCR under larger current conditions. In addition, the phenomenon in TLP results is consistent with simulation results. The proposed LDMOS-SCR-R can effectively increase failure current without affecting the device’s design window, and the additional p-type region will not increase the layout area.&lt;/p&gt;
ER  -