TY  - JOUR
AU  - Barzdenas, V.
AU  - Poviliauskas, D.
AU  - Grazulevicius, G.
AU  - Kiela, K.
PY  - 2012/06/07
Y2  - 2025/01/02
TI  - Design of an 8-bit 1GS/s F&I ADC in 0,13µm SiGe BiCMOS Technology
JF  - Elektronika ir Elektrotechnika
JA  - ELEKTRON ELEKTROTECH
VL  - 122
IS  - 6
SE  - 
DO  - 10.5755/j01.eee.122.6.1821
UR  - https://eejournal.ktu.lt/index.php/elt/article/view/1821
SP  - 55-58
AB  - In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolating analog-digital converter (F&I ADC) are presented. The converter for four lower bits used folding with interpolation whose coefficients respectively equal to 8 and 6, and four upper bits made using parallel comparators structure. ADC design and simulations carried out with Cadence software packages. Dynamic characteristics of the converter are presented, which shows that signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at 1 MHz input signal and 1 GS/s clock frequency is respectively equal to 49,7/54,6 dB. It is also identified effective number of bits (ENOB), which is approximately equal to 8-bit, when the input signal frequency is 1 MHz and at 500 MHz, ENOB drops to around 6-bit. After static characteristics simulation were got that the differential nonlinearity (DNL) did not exceed ±0,4 LSB and integral nonlinearity (INL) is less than ±0,6 LSB. Ill. 8, bibl. 6, tabl. 1 (in English; abstracts in English and Lithuanian).<p>DOI: <a href="http://dx.doi.org/10.5755/j01.eee.122.6.1821">http://dx.doi.org/10.5755/j01.eee.122.6.1821</a></p>
ER  -