TY  - JOUR
AU  - Morkunas, K.
AU  - Seinauskas, R.
PY  - 2011/06/08
Y2  - 2025/01/02
TI  - Verification of Initialization Sequences for Sequential Circuits
JF  - Elektronika ir Elektrotechnika
JA  - ELEKTRON ELEKTROTECH
VL  - 112
IS  - 6
SE  - 
DO  - 10.5755/j01.eee.112.6.446
UR  - https://eejournal.ktu.lt/index.php/elt/article/view/446
SP  - 61-64
AB  - This article suggests an approach for verification of initializing sequences. Such sequences were discovered using circuit emulating software prototypes. Software prototypes operate using bivalent logics (0 and 1), while hardware testing employs ternary logic (0, 1 and X). Experimental results show, that validation using ternary logic is too strict, labeling good initializing sequences as bad ones. Experimental results are based on ISCAS'89 benchmark. Ill. 1, bibl. 12, tabl. 3 (in English; abstracts in English and Lithuanian).<p><a href="http://dx.doi.org/10.5755/j01.eee.112.6.446">http://dx.doi.org/10.5755/j01.eee.112.6.446</a></p>
ER  -